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The RAM included in the processor unit provides an automatic double inverted memory function for detection of arbitrary bit errors in the memory.
• All memory updates are written to both the primary memory and to the inverted memory in parallel.
• At every memory read cycle, the data from tho two memories is compared.
• If there is a mismatch in the data a changeover is forced.
The double inverted memory handling is done in hardware and without any delay to the memory cycle time.
ABB DSPC 153
DSPC 153 | ABB | Processor Module
This means that a redundant controller will be always identified and recognized by the same addresses regardless of which CPU module actually acting as primary
The addresses of the initial primary CPU are stored and kept as the addresses used by the acting primary CPU
| ABB | ||
| EI803F 3BDH000017R1 | SS822 3BSC610042R1 | |
| PHBFIO10010000 FIO 100 P-HB-FIO-10010000 | AO815 3BSE052605R1 | |
| EI813F 3BDH000022R1 | TU830V1 3BSE013234R1 | |
| DCA2000A | PHCBRC30000000 BRC300 | |
| P-HA-MCL-110RB000 | IMASO11 | |
| HP-HP/AA-7676-91-0050 | INTCT12 | |
| TC562 3BSC630049R1 | INNIS11 | |
| SD811V1 3BSC610044R1 | NTAI05 | |
| PHAFIOFFH10000 WE-EN-01-161 | SA801F 3BDH000011R1 | |
| REF542 | SA811F 3BDH000013R1 | |
| C100/0000/STDCE | DDI01 P3711-4-0369626 | |
| ICSI16D1 | DLM02 P37421-4-0338434 | |
| 1TG6302076R0001 | DCP02 P37211-4-0369654 | |
| 3DDE 300 404 CMA 124 | SD811V1 3BSE013231R1 | |
| 3DDE 300 402 CMA 122 | FI830F 3BDH000032R1 | |
| 3DDE 300 403 CMA 123 | TU840 3BSE020846R1 | |
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